The invention relates to Hardware Design Language tools for the design of circuit components and determining the performance and logical correctness of the designed circuit components. Hardware Design Languages and Hardware Design Language tools transform high-level designs (e.g., functional specifications or functional-level logic such as Boolean expressions, truth tables, or standard macro logic) into its hardware implementation, and model the target system to predict its performance and analyze its behavior.
Tools for translating Hardware Description Languages (HDL) to gate level circuits are either behavioral or at the Register Transfer Level (RTL). These tools are deployed either for logic synthesis or cycle accurate simulation (software cycle simulators, accelerators, emulators, etc). For RTL tools, the architecture of the design is explicitly coded in the input HDL description, for example, an FSM is usually coded as a case statement, where the case choices are the states and the state transitions and other statements executions are described in the choice actions. For behavioral designs, the architecture is implicitly coded in the input HDL. One of the examples of behavioral constructs is the usage of multiple wait statements that can be embedded in control constructs (“if” and “case” statements) or loop constructs (“for” and “while” loops). Adding multiple wait support to RTL tools complicate the internal data structures and processing algorithms of these tools to an extent that these tools were not designed to perform such tasks. Thus, a clear need exist for methods and systems for preprocessing the multiple wait statements and synthesizing the multiple “wait” statements into constructs already supported by RTL tools.